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Verification by Error Modeling

:	Katarzyna Radecka, Zeljko Zilic
:	Verification by Error Modeling
:	Kluwer Academic Publishers
:	9780306487392
:	1
:	CHF 83.40
:

:	Naturwissenschaft
:	English

:	233
:	DRM
:	PC/MAC/eReader/Tablet
:	PDF

Verification presents the most time-consuming task in the integrated circuit design process. The increasing similarity between implementation verification and the ever-needed task of providing vectors for manufacturing fault testing is tempting many professionals to combine verification and testing efforts.

This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. The book brings the results in the direction of merging manufacturing test vector generation and verification. It first discusses error fault models suitable for approaching the verification by testing methods. Then, it elaborates a proposal for an implicit fault model that uses the Arithmetic Transform representation of a circuit and the faults. Presented is the fundamental link between the error size and the test vector size, which allows parametrizable verification by test vectors. Furthermore, the test vector set is sufficient not only for detecting, but also for diagnosing and correcting the design errors.

The practical use of any such simulation-based verification scheme can be seriously impaired by redundant faults, that otherwise require exhaustive simulations. The redundant fault identification methods are presented that are well suited for the type of faults considered. Finally, the same representation can be used to augment and expand the formal verification schemes that are to be used in conjunction with the simulation-based verification.

The primary audience forVerification by Error Modeling includes researchers in verification and testing, managers in charge of verification of test and practicing engineers. Due to its comprehensive coverage of background topics, the book can also be used for teaching courses on verification and test topics.

Writte for:
Researchers in verification and testing, managers in charge of verification of test and practicing engineers

	Contents	7
	List of Figures	11
	Acknowledgments	15
	Chapter 1 INTRODUCTION	16
	1. DESIGN FLOW	16
	2. VERIFICATION – APPROACHES AND PROBLEMS	19
	2.1 Verification Approaches	20
	2.2 Verification by Simulations	20
	2.3 Test Vector Generation	20
	2.4 Design Error Models	22
	2.5 Other Simulation Methods	24
	2.6 Formal Verification	26
	2.7 Model- based Formal Verification Methods	27
	2.8 Proof- theoretical Formal Verification Methods	29
	2.9 Spectral Methods in Verification	29
	3. BOOK OBJECTIVES	30
	Chapter 2 BOOLEAN FUNCTION REPRESENTATIONS	34
	1. BACKGROUND - FUNCTION REPRESENTATIONS	34
	1.1 Truth Tables	35
	1.2 Boolean Equations - Sum of Products	36
	1.3 Satisfiability of Boolean Functions	38
	1.4 Shannon Expansion	43
	1.5 Polynomial Representation	43
	2. DECISION DIAGRAMS	45
	2.1 Reduced Ordered Binary Decision Diagrams	46
	2.2 Word- Level Decision Diagrams	48
	3. SPECTRAL REPRESENTATIONS	53
	3.1 Walsh- Hadamard Transform	54
	3.2 Walsh Transform Variations	55
	3.3 Walsh-Hadamard Transform as Fourier Transform	56
	4. ARITHMETIC TRANSFORM	59
	4.1 Calculation of Arithmetic Transform	62
	4.2 AT and Word- Level Decision Diagrams	64
	Chapter 3 DON’T CARES AND THEIR CALCULATION	66
	1. INCOMPLETELY SPECIFIED BOOLEAN FUNCTIONS	66
	1.1 Don’t Cares in Logic Synthesis	66
	1.2 Don’t Cares in Testing for Manufacturing Faults	67
	1.3 Don’t Cares in Circuit Verification	69
	2. USING DON’T CARES FOR REDUNDANCY IDENTIFICATION	70
	2.1 Basic Definitions	71
	2.2 Calculation of All Don’t Care Conditions	72
	2.3 Algorithms for Computing ODCs	80
	2.4 Approximations to Observability Don’t Cares - CODCs	82
	Chapter 4 TESTING	86
	1. INTRODUCTION	86
	2. FAULT LIST REDUCTION	88
	3. OVERVIEW OF SIMULATORS	88
	3.1 True- Value Simulator Types	89
	3.2 Logic Simulators	90
	4. FAULT SIMULATORS	94
	4.1 Random Simulations	96
	5. DETERMINISTIC VECTOR GENERATION – ATPG	109
	5.1 Deterministic Phase	109
	5.2 Search for Vectors	113
	5.3 Fault Diagnosis	115
	6. CONCLUSIONS	116
	Chapter 5 DESIGN ERROR MODELS	118
	1. INTRODUCTION	118
	2. DESIGN ERRORS	120
	3. EXPLICIT DESIGN ERROR MODELS	122
	3.1 Detecting Explicit Errors	125
	4. IMPLICIT ERROR MODEL PRECURSORS	127
	4.1 Rationale for Implicit Models	128
	4.2 Related Work – Error Models	129
	5. ADDITIVE IMPLICIT ERROR MODEL	130
	5.1 Arithmetic Transform of Basic Design Errors	132
	6. DESIGN ERROR DETECTION AND CORRECTION	138
	6.1 Path Trace Procedure	140
	6.2 Back- propagation	141
	6.3 Boolean Difference Approximation by Simulations	142
	7. CONCLUSIONS	143
	Chapter 6 DESIGN VERIFICATION BY AT	144
	1. INTRODUCTION	144
	2. DETECTING SMALL AT ERRORS	147
	2.1 Universal Test Set	147
	2.2 AT- based Universal Diagnosis Set	148
	3. BOUNDING ERROR BY WALSH TRANSFORM	150
	3.1 Spectrum Comparison	152
	3.2 Spectrum Distribution and Partial Spectra Comparison	153
	3.3 Absolute Value Comparison	155
	4. EXPERIMENTAL RESULTS	157
	5. CONCLUSIONS	161
	Chapter 7 IDENTIFYING REDUNDANT GATE AND WIRE REPLACEMENTS	162
	1. INTRODUCTION	162
	2. GATE REPLACEMENT FAULTS	164
	2.1 Redundant Replacement Faults	165
	3. REDUNDANCY DETECTION BY DON’T CARES	166
	3.1 Using Local Don’t Cares	167
	3.2 Using Testing - Single Minterm Approximation	169
	3.3 Redundant Single Cube Replacements	174
	4. EXACT REDUNDANT FAULT IDENTIFICATION	178
	5. IDENTIFYING REDUNDANT WIRE REPLACEMENTS	179
	5.1 Wire Replacement Faults and Rewiring	181
	5.2 Detection by Don’t Cares	182
	5.3 Don’t Care Approximations	184
	5.4 SAT for Redundant Wire Identification	185
	6. EXACT WIRE REDUNDANCY IDENTIFICATION	187
	7. I/O PORT REPLACEMENT DETECTION	190
	7.1 Detection of I/ O Port Wire Switching Errors	190
	8. EXPERIMENTAL RESULTS	192
	8.1 Gate Replacement Experiments	192
	8.2 Wire Replacement Experiments	197
	8.3 SAT vs. ATPG	200
	9. CONCLUSIONS	200
	Chapter 8 CONCLUSIONS AND FUTURE WORK	202
	1. CONCLUSIONS	202
	2. FUTURE WORK	204
	Appendicies	206
	References	212
	Index	226