The Verillog® Hardware Description Language
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Donald E. Thomas, Philip R. Moorby
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The Verillog® Hardware Description Language
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Kluwer Academic Publishers
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9780306476662
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5
:
CHF 78.10
:
:
Sonstiges
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English
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402
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DRM
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PC/MAC/eReader/Tablet
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PDF
This text presents the IEEE 1364-2001 standard of the Verilog language. The examples in this edition have been updated to illustrate the features of the language. A cross referenced guide to these features is provided, thus, designers already familiar with Verilog can quickly learn the features. Newcomers to the language can use it as a guide for reading"old" specifications. The book should prove to be a useful resource for engineers and students interested in describing, simulating and synthesizing digital systems. It is also ready for use in university courses, having been used for introductory logic design and simulation through advanced VLSI design courses. An appendix with tutorial help and a work-along style is keyed into the introduction for new students. Material supporting a computer-aided design course on the inner working of simulators is also included.
2 Logic Synthesis
(p. 35-36)
In this chapter, the use of the language as an input specification for synthesis is presented. The concern is developing a functionally correct specification while allowing a synthesis CAD tool to design the final gate level structure of the system. Care must be taken in writing a description so that it can be used in both simulation and synthesis.
2.1 Overview of Synthesis
The predominate synthesis technology in use today is logic synthesis. A system is specified at the register-transfer level of design; by using logic synthesis tools, a gate level implementation of the system can be obtained. The synthesis tools are capable of optimizing a design with respect to various constraints, including timing and/or area. They use a technology library file to specify the components to be used in the design.
2.1.1 Register-Transfer Level Systems
A register-transfer level description may contain parts that are purely combinational while others may specify sequential elements such as latches and flip flops. There may also be a finite state machine description, specifying a state transition graph.
A logic synthesis tool compiles a register-transfer level design using two main phases. The first is a technology independent phase where the design is read in and manipulated without regard to the final implementation technology. In this phase, major simplifications in the combinational logic may be made. The second phase is technology mapping where the design is transformed to match the components in a component library. If there are only two-input gates in the library, the design is transformed so that each logic function is implementable by a component in the library. Indeed, synthesis tools can transform one gate level description into another, providing the capability of redesigning a circuit when a new technology library is used. The attraction of a logic synthesis CAD tool is that it aids in a very complex design process. (After all, did your logic design professor ever tell you what to do when the Karnaugh map had more than five or six variables!) These tools target large combinational design and different technology libraries, providing implementation trade-offs in time and area. Further, they promise functional equivalence of the initial specification and its resulting implementation. Given the complexity of this level of design, these tools improve the productivity of designers in many common design situations. To obtain this increased productivity, we must specify our design in a way that it can be simulated for functional correctness and then synthesized. This chapter discusses methods of describing register-transfer level systems for input to logic synthesis tools.
2.1.2 Disclaimer
The first part of this chapter defines what a synthesizable description for logic synthesis is. There are behaviors that we can describe but that common logic synthesis tools will not be able to design. (Or they may design something you’d want your competitor to implement!) Since synthesis technology is still young, and the task of mapping an arbitrary behavior on to a set of library components is complex, arbitrary behavior specifications are not allowed as inputs to logic synthesis tools. Thus, only a subset of the language may be used for logic synthesis, and the style of writing a description using that subset is restricted. The first part of this chapter describes the subset and restrictions commonly found in logic synthesis specification today. Our discussion of logic synthesis is based on experience using current tools. If you use others, your mileage may vary. Read the synthesis tool manual closely.
Content
7
Preface
15
From the Old to the New
17
Acknowledgments
21
1 Verilog - A Tutorial Introduction
22
Getting Started
23
Behavioral Modeling of Combinational Circuits
32
Procedural Modeling of Clocked Sequential Circuits
35
Module Hierarchy
42
Summary
48
Exercises
49
2 Logic Synthesis
56
Overview of Synthesis
56
Combinational Logic Using Gates and Continuous Assign
58
Procedural Statements to Specify Combinational Logic
61
Inferring Sequential Elements
69
Inferring Tri-State Devices
73
Describing Finite State Machines
74
Finite State Machine and Datapath
79
Summary on Logic Synthesis
87
Exercises
89
3 Behavioral Modeling
94
Process Model
94
If-Then-Else
96
Loops
103
Multi-way Branching
107
Functions and Tasks
112
Rules of Scope and Hierarchical Names
123
Summary
127
Exercises
127
4 Concurrent Processes
130
Concurrent Processes
130
Events
132
The Wait Statement
137
A Concurrent Process Example
143
A Simple Pipelined Processor
149
Disabling Named Blocks
153
Intra-Assignment Control and Timing Events
155
Procedural Continuous Assignment
157
Sequential and Parallel Blocks
159
Exercises
161
5 Module Hierarchy
164
Module Instantiation and Port Specifications
164
Parameters
167
Arrays of Instances
171
Generate Blocks
172
Exercises
175
6 Logic Level Modeling
178
Introduction
178
Logic Gates and Nets
179
Continuous Assignment
192
A Mixed Behavioral/Structural Example
197
Logic Delay Modeling
201
Delay Paths Across a Module
208
Summary of Assignment Statements
210
Summary
211
Exercises
212
7 Cycle-Accurate Specification
216
Cycle-Accurate Behavioral Descriptions
216
Cycle-Accurate Specification
219
Mealy/Moore Machine Specifications
224
Introduction to Behavioral Synthesis
230
Summary
231
8 Advanced Timing
