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Electronic System Level Design An Open-Source Approach

:	Luiz Santos, Rodolfo Azevedo, Sandro Rigo
:	Sandro Rigo, Rodolfo Azevedo, Luiz Santos
:	Electronic System Level Design An Open-Source Approach
:	Springer-Verlag
:	9781402099403
:	1
:	CHF 85.40
:

:	Elektronik, Elektrotechnik, Nachrichtentechnik
:	English

:	146
:	Wasserzeichen
:	PC/MAC/eReader/Tablet
:	PDF

Electronic System Level Design: an Open-Source Approach is based on the successful experience acquired with the conception of the ADL ArchC, the development of its underlying tool suite, and the building of its platform modeling infrastructure. With more than 10000 accesses per year since 2004, the dissemination of ArchC models reached not only students in quest of proper infrastructure to develop their research projects but also some companies in need of processor models to build virtual platforms using SystemC.

The need to anticipate the development of hardware-dependent software and to build virtual prototypes gave rise to Transaction Level Modeling (TLM). Since SystemC provided the elements and the adequate abstraction level for supporting TLM, their relation has grown so strong that OSCI created a TLM Working Group whose effort resulted in the recently released TLM 2.0 standard, which is also covered in this book.

	Preface	5
	Contents	7
	Contributors	8
	Part I: System Design Representation	9
	Chapter 1: Electronic System Level Design	10
	1.1 The ESL Concept	10
	1.2 Requirements of an ESL Representation	11
	1.3 ESL Design Flow	12
	1.4 Target Audience, Scope and Organization	15
	References	16
	Chapter 2: Open-Source Languages	18
	2.1 Basic SystemC Concepts	18
	2.2 Introduction to ArchC	23
	2.2.1 Architecture Resources Description	25
	2.2.2 Instruction Set Architecture Description	26
	ISA Specification	26
	Instruction Behavior Description	28
	2.2.3 The Evolution of ArchC Towards Platform Modeling	30
	References	31
	Chapter 3: Transaction Level Modeling	32
	3.1 Introduction	32
	3.2 The Evolution Towards the OSCI TLM 2.0 Standard	34
	3.3 Main Features in the TLM 2.0 Standard	35
	3.4 A Small TLM Platform Example	38
	References	43
	Part II: Open-Source Models and Tools	44
	Chapter 4: ArchC Model Design Handbook	45
	4.1 What Is a Model?	45
	4.2 Start Modeling-Architectural Information	46
	4.3 Declaring Instructions	49
	4.4 Implementing Instructions	53
	4.5 Running the Simulator	58
	4.6 Debugging the Model-First Steps	60
	4.6.1 Using the GDB Interface	60
	4.6.2 Implementing the GDB Interface	61
	4.7 Compiler and Operating System Support	69
	4.7.1 The Helper Methods	70
	4.7.2 ABI Stub Library	72
	4.7.3 Startup File	73
	4.8 Refining the Model	73
	4.9 Going Faster-How to Improve Your Simulator Performance	74
	References	75
	Chapter 5: Building Platform Models with SystemC	77
	5.1 ArchC and TLM Interface	78
	5.2 Platforms with ArchC	80
	5.3 Platform Examples	81
	5.3.1 A Processor-Memory Platform	81
	5.3.2 Dual Core Platform	84
	5.4 The MP3 Example	90
	5.4.1 Profiling	90
	5.4.2 Moving the Code to the Platform	93
	5.4.3 Building the Hardware/Software Interface	93
	5.4.4 The Next Steps Towards Parallel Software	101
	Chapter 6: Retargetable Binary Tools	105
	6.1 Introduction	105
	6.2 Language Support for Binary Tools	107
	6.2.1 Assembly Language Symbols	108
	6.2.2 Instruction Syntax and Operand Encoding	108
	6.2.3 Instruction Encoding and Modifiers	109
	6.2.4 Pseudo Instructions	112
	6.3 Binary Tools Retargeting	113
	6.3.1 GNU Binutils Package	113
	6.3.2 Automatic Binutils Retargeting	114
	6.3.3 Opcodes Library Generation	115
	6.3.4 BFD Library Generation	115
	6.3.5 Assembler Generation	116
	6.3.6 Link Editor Generation	116
	6.3.7 Summary of Generated Files	118
	6.4 Putting it to Work	118
	References	120
	Part III: Advanced Topics	121
	Chapter 7: Debugging SystemC Platform Models	122
	7.1 Introduction	122
	7.2 Model Debugging and Verification in SystemC	123
	7.3 Why Computational Reflection?	124
	7.4 Enabling Data Introspection in SystemC	125
	7.5 Debugging a Platform Simulation Model	127
	References	133
	Chapter 8: SystemC-Based Power Evaluation with PowerSC	134
	8.1 SystemC Extensions for Power Modeling	134
	8.1.1 The Extended Design Flow	135
	8.1.2 The SystemC Extensions	136
	8.2 Instrumentation of a SystemC Description	137
	8.3 Support for Characterization at the Gate Level	138
	8.3.1 Integration of Macromodels in PowerSC	139
	8.4 Putting PowerSC to Work	145
	8.4.1 Downloading	145
	8.4.2 Checking Requirements	146
	8.4.3 Building the Packages	146
	Building PowerSC	146
	Building PSCLibTools	147
	Building Lib2PSCLib	147
	8.4.4 Running PowerSC	148
	References	149
	Index	150