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Voltage Regulators for Next Generation Microprocessors

:	Toni López, Reinhold Elferich, Eduard Alarcón
:	Voltage Regulators for Next Generation Microprocessors
:	Springer-Verlag
:	9781441975607
:	1
:	CHF 94.80
:

:	Elektronik, Elektrotechnik, Nachrichtentechnik
:	English

:	401
:	Wasserzeichen
:	PC/MAC/eReader/Tablet
:	PDF

This book deals with energy delivery challenges of the power processing unit of modern computer microprocessors. It describes in detail the consequences of current trends in miniaturization and clock frequency increase, upon the power delivery unit, referred to as voltage regulator. This is an invaluable reference for anybody needing to understand the key performance limitations and opportunities for improvement, from both a circuit and systems perspective, of state-of-the-art power solutions for next generation CPUs.

	Voltage Regulators for Next Generation Microprocessors	3
	Preface	7
	Abstract	11
	Contents	13
	Abbreviations	19
	Chapter 1: Introduction	27
	1.1 The Microprocessor Load	27
	1.2 The Microprocessor Power Supply	35
	1.2.1 Voltage Regulator (VR) Specifications	35
	1.2.1.1 VR Guidelines for Servers and Workstations	38
	1.2.1.2 VR Guidelines for Notebooks	38
	1.2.1.3 The DrMOS Specification	39
	1.2.2 Basic Circuit Topology	39
	1.2.3 System Architecture	41
	1.2.4 Semiconductor Power Devices	43
	1.2.4.1 Device Modeling and Optimization Tools	47
	1.2.5 Gate Driving Schemes	48
	1.2.6 Filters	51
	1.2.6.1 Input Filter	52
	1.2.6.2 Output Filter	53
	1.2.7 Control Systems	57
	1.2.7.1 Load Line Regulation	58
	1.2.7.2 Multiphase Regulation	61
	1.2.7.3 Multimode Switching Modulation	63
	1.2.7.4 Gate Driving Control	63
	1.2.8 Packaging and Integration	65
	1.2.9 Commercial Voltage Regulators	67
	1.2.10 Survey on Power MOSFET Models for Circuit Simulations	71
	1.3 Objectives of the Thesis	74
	1.4 Methodological Approach	75
	1.5 Thesis Outline	79
	References	80
	Chapter 2: Model Level 0: Switching Behavior of Power MOSFETs	92
	2.1 Power MOSFET Model for Circuit Simulations	93
	2.1.1 Model Structure and Implementation	94
	2.1.2 Model Data Acquisition	100
	2.1.2.1 Gate Resistance and Package Impedances	100
	2.1.2.2 DC Output Characteristics	105
	2.1.2.3 Interelectrode Capacitances	107
	2.1.2.4 Body Diode Reverse Recovery	112
	2.2 Switched Converter Test Board	115
	2.2.1 Gate Driver	116
	2.2.2 Input/Output Filters	119
	2.2.3 PCB Layout Impedance Characterization	120
	2.3 Switched Converter Simulation Setup	122
	2.4 Model Validation	126
	2.5 Analysis of Switching Behavior	137
	2.5.1 Loss Breakdown	138
	2.5.1.1 Switching Time Subintervals	139
	CHS and RR at LE Transition (t1-t3)	141
	VHS at LE Transition (t3-t4)	142
	VHS at FE Transition (t5-t6)	143
	CHS at FE Transition (t6-t7)	143
	2.5.1.2 Identification of Switching Loss Mechanisms	143
	Load Current Hard-Switching (or Snubbed Hard-Switching SHS)	143
	Half-Bridge Charging (Both Capacitive and Inductive)	144
	Gate Charging	144
	Reverse Recovery	144
	Gate Bounce	145
	Avalanche Breakdown	145
	2.5.1.3 Loss Quantification	145
	2.5.2 Influence of the Body-Effect on Switching Losses	147
	2.5.2.1 Impact on Reverse Recovery	149
	2.5.2.2 Impact on Gate Bounce	151
	2.5.3 Loss Analysis of a Multichip Module	153
	References	156
	Chapter 3: Model Level 1: Piecewise Linear Analytical Switching Model	158
	3.1 Modeling Approach	159
	3.2 Hard-Switching Model	166
	3.2.1 Leading Edge Transition	168
	3.2.2 Falling Edge Transition	172
	3.2.3 Leading and Falling Edge Transitions Tradeoffs	175
	3.3 Leading Edge Switched-Node Ringing	180
	3.3.1 Charging Loss	184
	3.3.2 Overvoltage Stress	186
	3.3.3 Avalanche Breakdown	187
	3.3.4 Reverse Recovery	191
	3.3.5 Gate Bounce	194
	3.4 Falling Edge Ringing Transition	205
	3.4.1 Charging Loss	209
	3.4.2 Overvoltage Stress	213
	3.4.3 Avalanche Breakdown	215
	3.5 Gate Driving	215
	3.6 Model Validation	216
	References	220
	Chapter 4: Model Level 2: Power Loss Model	221
	4.1 Power MOSFET Losses	222
	4.1.1 Half-Bridge Charging Loss	222
	4.1.2 Gate Charging Loss	223
	4.1.3 Load Current Hard-Switching	225
	4.1.3.1 LE Transition	226
	4.1.3.2 FE Transition	227
	4.1.4 Load Current ON Conduction	229
	4.2 Losses of Gate Drive Switches	231
	4.3 Filter Loss	232
	4.4 PCB Loss	233
	4.5 Model Validation	234
	References	236
	Chapter 5: Model Level 3: Optimization	237
	5.1 Output Filter	237
	5.1.1 Steady-State Output Ripple	238
	5.1.2 Load Line Transient	241
	5.1.2.1 Output Current Slew Rate	243
	5.1.2.2 Output Inductors´ Discharge	244
	5.1.3 Component Selection Procedure	247
	5.2 Input Filter	250
	5.3 Power MOSFETs and Gate Drivers	252
	5.3.1 Design Guidelines	255
	5.3.2 Optimization Case Example	256
	5.4 Selection of Fs, Lo, and Np	259
	5.4.1 Case-Example 1: State-of-the-Art Desktop Application	259
	5.4.2 Case Example 2: State-of-the-Art Laptop Application	263
	References	267
	Chapter 6: Roadmap Targets	268
	6.1 Power Switches	269
	6.1.1 State-of-the-Art Trench4 MOSFET Technology	270
	6.1.2 Trench6 MOSFET Technology	276
	6.1.3 Next Generation Technologies	283
	6.2 Gate Drivers	286
	6.3 Packaging	289
	6.4 Passive Filters	289
	6.5 Control	291
	6.6 Layout Arrangement	292
	6.7 Mobile Laptop Applications	298
	References	300
	Chapter 7: Conclusions and Future Work	302
	Appendix A: Third Quadrant DC Output Character