: Hong Dongwoo, Kwang-Ting Cheng
: Efficient Test Methodologies for High-Speed Serial Links
: Springer-Verlag
: 9789048134434
: 1
: CHF 123.50
:
: Sonstiges
: English
: 98
: Wasserzeichen
: PC/MAC/eReader/Tablet
: PDF

Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.
Efficient Test Methodologiesfor High-Speed Serial Links1
1 Introduction11
1.1 Overview of High-Speed Serial Links11
1.1.1 High-Speed Serial Link System11
1.1.2 Testing High-Speed Serial Links12
1.2 Challenges in Testing High-Speed Serial Links13
1.3 Contributions of the Dissertation14
2 An Efficient Jitter Measurement Technique16
2.1 Comparator Undersampling Technique16
2.2 Random Jitter Measurement18
2.2.1 Proposed RJ Measurement Technique19
2.2.2 Limitations of the Technique21
2.3 Experimental Results22
2.3.1 Simulation Results23
2.3.1.1 Simulation: Case 123
2.3.1.2 Simulation: Case 223
2.3.1.3 Simulation: Case 324
2.3.2 Measurement Results25
2.3.2.1 Experiment: Case 125
2.3.2.2 Experiment: Case 226
2.4 Summary27
3 BER Estimation for Linear Clock and Data Recovery Circuit28
3.1 BER Analysis with Random Jitter29
3.1.1 Error Occurrences29
3.1.2 BER Estimation with Random Jitter29
3.2 BER Analysis with Random Jitter and Periodic Jitter31
3.2.1 Jitter Transfer Characteristics of a CDR Circuit32
3.2.2 BER Estimation with RJ and PJ34
3.2.2.1 Dual-Dirac Model and Its Modification34
3.2.2.2 BER Estimation Taking into Account Clock Recovery Function35
3.3 BER Analysis Including Intrinsic Noise in the CDR Circuit41
3.4 Experimental Results43
3.4.1 Simulation Results43
3.4.2 Hardware Validation Results44
3.4.2.1 Jitter Transfer Characteristics45
3.4.2.2 BER Measurement Results47
3.5 Summary and Future Work49
4 BER Estimation for Non-linear Clock and Data Recovery Circuit50
4.1 Jitter Analysis for BB CDR Circuits50
4.1.1 Jitter Transfer Analysis51
4.1.2 Jitter Tolerance Analysis54
4.2 BER Estimation54
4.2.1 Variation of Jitter Transfer Due to RJ55
4.2.2 BER Estimation57
4.3 Experimental Setup and Results58
4.3.1 Simulation Setup58
4.3.2 Simulation Results59
4.4 Summary60
5 Gaps in Timing Margining Test61
5.1 Timing Margining Test Basics61
5.2 Gap Analysis in Timing Margining Test62
5.2.1 Random Jitter63
5.2.2 PLL-Based Clock Recovery with Non-linear Phase Detector64
5.2.3 Jitter Amplification67
5.2.4 Duty Cycle Distortion in Clock69
5.3 Summary and Future Work71
6 An Accurate Jitter Estimation Technique73
6.1 Characteristics of DJ73
6.1.1 ISI-Induced Jitter74
6.1.2 Crosstalk-Induced Jitter74
6.2 Total Jitter Estimation76
6.2.1 Estimation Based on Dual-Dirac Model76
6.2.2 High-Order Polynomial Fitting79
6.2.3 Accuracy Versus Number of Samples for Fitting79
6.3 Summary80
7 A Two-Tone Test Method for Continuous-Time Adaptive Equalizers82
7.1 Continuous-Time Adaptive Equalizer83
7.2 Proposed Two-Tone Test Method85
7.2.1 Description of the Test Method85
7.2.2 Implementation of the Test Method86
7.3 Experimental Results89
7.3.1 MATLAB Simulation Results89
7.3.2 Transistor-Level Simulation Results91
7.4 Summary and Future Work92
8 Conclusions95
A Extracting Effective PJ and RJ Components from Jitter Histogram97
References100