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Advanced Test Methods for SRAMs Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies

:	Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
:	Advanced Test Methods for SRAMs Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies
:	Springer-Verlag
:	9781441909381
:	1
:	CHF 87.10
:

:	Elektronik, Elektrotechnik, Nachrichtentechnik
:	English

:	171
:	Wasserzeichen
:	PC/MAC/eReader/Tablet
:	PDF

Modern electronics depend on nanoscaled technologies that present new challenges in terms of testing and diagnostics. Memories are particularly prone to defects since they exploit the technology limits to get the highest density. This book is an invaluable guide to the testing and diagnostics of the latest generation of SRAM, one of the most widely applied types of memory. Classical methods for testing memory are designed to handle the so-called 'static faults,' but these test solutions are not sufficient for faults that are emerging in the latest Very Deep Sub-Micron (VDSM) technologies. These new fault models, referred to as 'dynamic faults', are not covered by classical test solutions and require the dedicated test sequences presented in this book.

	Acknowledgements	4
	Advanced Test Solutions for Dynamic Faults in SRAM Memories	5
	Authors of the book:	5
	Summary and objective of the book:	5
	Contents	6
	General Introduction	9
	History	9
	SRAMs	10
	Test of SRAMs	10
	Organization of the Book	10
	Description of Each Chapter	11
	1 Basics on SRAM Testing	12
	1.1 Overview of Semiconductor Memories	12
	1.2 Typical Structure of an SRAM	14
	1.3 The Context of SRAM Testing	16
	1.3.1 Memory Model	17
	1.3.2 Fault Model Representation	18
	1.3.3 Fault Model Classification	19
	1.3.4 Test Solutions and Algorithms	23
	1.4 Test Generation	26
	1.5 Test Validation	28
	1.6 Conclusion	30
	2 Resistive-Open Defects in Core-Cells	31
	2.1 The SRAM Core-Cell	31
	2.1.1 Reading in the Core-Cell	31
	2.1.2 Writing in the Core-Cell	32
	2.2 Analysis of Resistive-Open Defects in the Core-Cell	33
	2.2.1 Defect Location	33
	2.2.2 Defect Incidence Analysis	33
	2.2.3 Simulation Set-Up and Results	36
	2.3 Analysis and Test of dRDF	37
	2.3.1 Functional Fault Modeling of dRDF	38
	2.3.2 RES: Read Equivalent Stress	39
	2.3.3 March Test Solutions Detecting dRDFs	43
	2.4 Analysis and Test of dDRF	47
	2.4.1 Functional Fault Modeling of dDRF	47
	2.4.2 Experiments	48
	2.4.2.1 dDRF Due to Defect Df4	50
	2.4.2.2 dDRF Due to Defects Df2 and Df3	52
	2.4.3 March Test Solution Detecting dDRFs	53
	2.5 Impact of Technology Scaling	55
	2.6 Conclusion	58
	3 Resistive-Open Defects in Pre-charge Circuits	59
	3.1 The SRAM Pre-charge Circuit	59
	3.2 Anal