: Patrick Girard, Nicola Nicolici, Xiaoqing Wen
: Patrick Girard, Nicola Nicolici, Xiaoqing Wen
: Power-Aware Testing and Test Strategies for Low Power Devices
: Springer-Verlag
: 9781441909282
: 1
: CHF 96.70
:
: Elektronik, Elektrotechnik, Nachrichtentechnik
: English
: 363
: Wasserzeichen/DRM
: PC/MAC/eReader/Tablet
: PDF

Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.
Summary and Objective of the Book5
About the Editors6
Preface8
Contents12
Contributors21
1 Fundamentals of VLSI Testing22
1.1 Introduction22
1.2 Fault Models26
1.3 Design for Testability28
1.3.1 Ad Hoc Methods28
1.3.2 Scan Design31
1.3.3 Built-In Self-Test32
1.3.4 Test Compression34
1.4 Logic Testing36
1.5 Memory Testing40
1.6 System-On-Chip Testing44
1.7 Summary and Conclusions46
References47
2 Power Issues During Test51
2.1 Introduction51
2.2 Power and Energy Basics53
2.2.1 Static Dissipation53
2.2.1.1 Reverse-Biased pn Junction Leakage Current54
2.2.1.2 Sub-threshold Leakage Current54
2.2.1.3 Gate Leakage Current55
2.2.1.4 Gate-Induced Drain Leakage Current56
2.2.2 Dynamic Dissipation57
2.2.2.1 Dynamic Dissipation Due to Charging and Discharging of Load Capacitors57
2.2.2.2 Dynamic Dissipation Due to Short-Circuit Current59
2.2.3 Total Power Dissipation60
2.2.4 Energy Dissipation60
2.3 Manufacturing Test Flow61
2.3.1 Characterization Test61
2.3.2 Production Test61
2.3.3 Burn-in Test61
2.3.4 Incoming Inspection62
2.3.5 Typical Test Flow62
2.4 Power Delivery Issues During Test63
2.4.1 Packaging64
2.4.2 Power Grid Issues66
2.4.3 Power Supply Noise66
2.4.3.1 Low-Frequency Power Droop67
2.4.3.2 Mid-Frequency Power Droop68
2.4.3.3 High-Frequency Power Droop68
2.4.3.4 Voltage Drop During At-Speed Scan69
2.5 Thermal Issues During Test70
2.6 Test Throughput Problem72
2.6.1 Limited Power Availability During Wafer Sort Test72
2.6.2 Reduction in Test Frequency During Package Test73
2.6.3 Constraint on Simultaneous Testing of Multiple Cores73
2.6.4 Noisy Power Supply During Wafer Sort Test73
2.7 Manufacturing Yield Loss74
2.7.1 ATE Timing Inaccuracy74
2.7.2 Application of Illegal Test Vectors75
2.8 Test Power Metrics and Estimation76
2.8.1 Power Metrics77
2.8.2 Modeling of Power and Energy Metrics77
2.8.3 Test Power Estimation79
2.9 Summary80
References81
3 Low-Power Test Pattern Generation84
3.1 Introduction84
3.2 Low-Power ATPG86
3.2.1 General Low-Power Test Generation86
3.2.2 Low-Shift-Power Scan Test Generation87
3.2.3 Low-Capture-Power Scan Test Generation88
3.2.3.1 Capture-Safety Checking91
3.2.3.2 LCP ATPG Technique 1: Reversible Backtracking93
3.2.3.3 LCP ATPG Technique 2: Clock Manipulation94
3.3 Low-Power Test Compaction97
3.3.1 Low-Power Dynamic Compaction97
3.3.2 Low-Power Static Compaction98
3.3.2.1 Low-Shift-Power Static Compaction98
3.3.2.2 Low-Capture-Power Static Compaction99
3.4 Low-Power X-Filling100
3.4.1 Test Cube Preparation101
3.4.1.1 Direct Generation101
3.4.1.2 Test Relaxation102
3.4.2 Low-Shift-Power X-Filling106
3.4.2.1 Shift-In Power Reduction107
3.4.2.2 Shift-Out Power Reduction108
3.4.2.3 Total Shift Power Reduction108
3.4.3 Low-Capture-Power X-Filling109
3.4.3.1 FF-Oriented X-Filling109
3.4.3.2 Node-Oriented X-Filling114
3.4.3.3 Critical-Area-Oriented X-Filling116
3.4.4 Low-Shift-and-Capture-Power X-Filling116
3.4.4.1 Impact-Oriented X-Filling117
3.4.