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Analog Circuit Design Smart Data Converters, Filters on Chip, Multimode Transmitters

:	Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund
:	Arthur van Roermund, Herman Casier, Michiel Steyaert
:	Analog Circuit Design Smart Data Converters, Filters on Chip, Multimode Transmitters
:	Springer-Verlag
:	9789048130832
:	1
:	CHF 134.80
:

:	Elektronik, Elektrotechnik, Nachrichtentechnik
:	English

:	342
:	Wasserzeichen
:	PC/MAC/eReader/Tablet
:	PDF

Analog Circuit Design contains the contribution of 18 tutorials of the 18^th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 18 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of: Smart Data Converters: Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology, Filters on Chip: Chaired by Herman Casier, AMI Semiconductor Fellow, Multimode Transmitters: Chaired by Prof. M. Steyaert, Catholic University Leuven, Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design.

Prof. Arthur van Roermund and Prof. Michiel Steyaert have been editing the best papers from the yearly Advances in Analog Circuit Design workshop into a book for the past 5 years. Dr. Herman Casier is new to the editing trio, he brings excellent input from industry.

	Analog Circuit Design	244
	1	244
	Preface	244
	4	244
	Series on Integrated Circuits and Systems	4
	Part I Smart Data Converters	8
	1 LMS-Based Digital Assisting for Data Converters	9
	1.1 Introduction	9
	1.2 High-Resolution ADCs	10
	1.3 Limits of ADC Resolution	13
	1.4 Zero-Forcing LMS Algorithm	14
	1.5 LMS-Based Calibration of the Pipelined ADC	15
	1.5.1 Measurement Time and Dither Magnitude Constraints	16
	1.5.2 Signal-Dependent Dithering Under Two Constraints	17
	1.5.3 Linearity Improvement	19
	1.5.4 Opamp Non-linearity Calibration	20
	1.6 Noise Leakage Calibration in CT Cascaded Modulator	21
	1.6.1 CT-to-DT Transform	22
	1.6.2 Calibrated Cascaded Modulator	23
	1.7 Conclusions	25
	References	26
	2 Pipelined ADC Digital Calibration Techniques and Tradeoffs	28
	2.1 Introduction	28
	2.2 Review of Error Sources in Pipelined ADCs	29
	2.2.1 Gain Errors	29
	2.2.2 DAC Errors	31
	2.3 Digital Calibration Techniques	31
	2.3.1 Digital Gain Error Calibration	32
	2.3.2 DAC Gain Error Calibration	32
	2.3.3 Foreground Calibration Techniques	33
	2.3.4 Background Calibration	34
	2.4 Rapid Background Calibration Techniques	35
	2.4.1 Slow but Accurate Parallel ADC	35
	2.4.2 Split-ADC Gain Error Calibration	36
	2.4.3 Rapid DAC and Gain Error Correction	37
	2.5 Using Digital Calibration to Build Low Power `Smart-ADCs'	41
	2.5.1 Open Loop, Non-linear Gain Error Calibration	41
	2.5.2 Capacitive Charge Pump Based Pipelined ADC	43
	2.6 Summary	46
	References	46
	3 High-Resolution and Wide-Bandwidth CMOS Pipeline AD Converters	48
	3.1 Introduction	48
	3.2 Digital Calibration of Non-Linearity	50
	3.2.1 DAC Non-linearity	51
	3.2.2 Stage Gain Non-linearity	52
	3.3 Range-Scaling in the First Pipeline Stage	53
	3.3.1 Power Consumption in a Noise-Limited ADC	53
	3.3.2 Circuit Implementation	54
	3.4 SHA-Less Architecture	55
	3.5 A 1.2V 14b 100MS/s ADC in 90nm CMOS	56
	3.5.1 ADC Architecture	57
	3.5.2 Measured Results	58
	3.6 Conclusions	63
	References	63
	4 A Signal Processing View on Time-Interleaved ADCS	65
	4.1 Introduction	65
	4.2 Time-Interleaved ADCs	66
	4.3 Modeling Time-Interleaved ADCs	67
	4.4 Digital Calibration of Linear Channel Mismatches	70
	4.4.1 Digital Correction Methods	71
	4.4.1.1 Time Offset Mismatches	72
	4.4.1.2 Frequency Response Mismatches	75
	4.4.2 Digital Identification Methods	77
	4.4.2.1 Off-line Identification	78
	4.4.2.2 On-line Identification	79
	4.5 Conclusions	81
	References	81
	5 DAC Correction and Flexibility, Classification, New Methods and Designs	83
	5.1 Introduction	83
	5.2 Correction Methods for Current-Steering DACs	84
	5.2.1 Classification	84
	5.2.2 New Correction Methods Based on Parallel Sub-DACs	87