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ESL Models and their Application Electronic System Level Design and Verification in Practice

:	Brian Bailey, Grant Martin
:	ESL Models and their Application Electronic System Level Design and Verification in Practice
:	Springer-Verlag
:	9781441909657
:	1
:	CHF 85.50
:

:	Elektronik, Elektrotechnik, Nachrichtentechnik
:	English

:	446
:	Wasserzeichen/DRM
:	PC/MAC/eReader/Tablet
:	PDF

This book arises from experience the authors have gained from years of work as industry practitioners in the field of Electronic System Level design (ESL). At the heart of all things related to Electronic Design Automation (EDA), the core issue is one of models: what are the models used for, what should the models contain, and how should they be written and distributed. Issues such as interoperability and tool transportability become central factors that may decide which ones are successful and those that cannot get sufficient traction in the industry to survive.

Through a set of real examples taken from recent industry experience, this book will distill the state of the art in terms of System-Level Design models and provide practical guidance to readers that can be put into use. This book is an invaluable tool that will aid readers in their own designs, reduce risk in development projects, expand the scope of design projects, and improve developmental processes and project planning.

	Preface	4
	Who Should Read This Book	5
	Structure of the Book	6
	Chapter Listing	7
	Relationship to First Book	9
	Companion Web Site	9
	Reference	10
	Acknowledgments	11
	Contents	12
	About the Authors	18
	About the Contributors	20
	1 Introduction	22
	1.1 A Definition of a Model	22
	1.2 A Day in the Life of a Model	5
	1.3 Types of Model	6
	1.4 Models of Computation	7
	1.5 Simplification	9
	1.5.1 Abstraction	31
	1.5.2 Structure	31
	1.6 Models and Languages	33
	1.6.1 Imperative Languages	33
	1.6.2 Declarative Languages	34
	1.6.3 Functional	35
	1.6.4 Non-functional	36
	1.6.5 Meta	37
	1.6.6 Testbench	38
	1.7 The Desire for a New Language	39
	1.8 Big Shoes to Fill	40
	1.8.1 Ptolemy Simulator	41
	1.8.2 SystemC	42
	1.8.3 Function and Interface	43
	1.9 Taxonomy	43
	1.9.1 Three New Axes	44
	1.9.1.1 Concurrency	44
	1.9.1.2 Communications	45
	1.9.1.3 Configurability	45
	1.9.2 Application to Models and Languages	46
	1.9.3 Transformation of Models	48
	1.10 Definitions	49
	References	52
	2 IP Meta-Models for SoC Assembly and HW/SW Interfaces	54
	2.1 Introduction	54
	2.2 IP Databases	54
	2.3 SPIRIT/IP-XACT	55
	2.3.1 History of SPIRIT	55
	2.3.2 RTL Assembly Level	58
	2.3.3 System Modeling Level	62
	2.4 Register Definition Languages	62
	2.4.1 Motivation: Modeling the HW/SW Interface	63
	2.4.1.1 What Is the HW/SW Interface?	63
	2.4.1.2 Hardware Configuration and Control Using Software	64
	2.4.1.3 Software Perspective	65
	2.4.1.4 Interrupts	67
	2.4.1.5 Software API	67
	2.4.1.6 Hardware Perspective	68
	2.4.1.7 Transaction Bus Protocol	69
	2.4.1.8 Protocol Translation	70
	2.4.1.9 Registers and Bitfields	72
	2.4.2 HW/SW Design Flow for HW/SW Interfaces	77
	2.4.2.1 Example IP Design -- The Requirements	78
	2.4.2.2 Specification -- Documentation	79
	2.4.2.3 IP-XACT (SPIRIT)	79
	2.4.2.4 SystemRDL	81
	2.4.2.5 IP Hardware Design	81
	2.4.2.6 IP Verification	84
	2.4.2.7 HDL Verification Environments	85
	2.4.2.8 HVL Environments	85
	2.4.2.9 VMM -- Verification Methodology Manual	86
	2.4.2.10 OVM -- Open Verification Methodology	87
	2.4.2.11 eRM '' Specman ''e'' Reuse Methodology	88
	2.4.2.12 OVM vs. VMM Interoperability	88
	2.4.2.13 Chip-Level Verification	88
	2.4.2.14 Software Development -- Firmware	91
	2.4.2.15 Firmware Verification	93
	2.4.2.16 RTL Models	94
	2.4.2.17 Virtual Models	94
	2.4.2.18 Earlier Software Development	94
	2.4.3 Emerging HW/SW Interface Tools and Design Flows	95
	2.4.3.1 Register Management Tools	96
	2.4.3.2 Case Study of a Register Management Solution: Bitwise	98
	2.5 Conclusions	101
	References	102
	3 Functional Models	104
	3.1 Dynamic Models and Languages	104
	3.1.1 Algorithmic Languages	105
	3.1.1.1 Mathematical Modeling Languages	105
	3.1.1.2 Example of MATLAB	106
	3.1.1.3 Example of C/C++ Reference Model	108
	3.1.1.4 Dataflow Modeling Languages	109
	3.1.1.5 Example of Simulink	110
	3.1.2 Architectural Modeling Languages: SystemC	112
	3.1.2.1 Scope of SystemC: Design Problems	112
	3.1.2.2 SystemC 2.0	114
	3.1.2.3 SystemC Language Basics	114
	3.1.2.4 SystemC in Real Systems	122
	3.1.2.5 Software System Specification	134
	3.1.2.6 TLM 2.0	138
	3.1.2.7 TLM Compliance Checking	149
	3.1.3 Architectural Models	155
	3.1.3.1 Modeling IP	155
	3.1.3.2 System Models for Architectural Exploration	156
	3.1.3.3 System Models for Software Development	158
	3.2 Formal Models	158
	3.2.1 Property Languages	158
	3.2.1.1 Uses of Declarative Languages	159
	3.2.1.2 Completeness	160
	References	162
	4 Testbench Models	163
	4.1 Testbench Basics	164
	4.1.1 Testbench C