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Creating Assertion-Based IP

:	Harry D. Foster, Adam C. Krolnik
:	Creating Assertion-Based IP
:	Springer-Verlag
:	9780387683980
:	1
:	CHF 94.90
:

:	Elektronik, Elektrotechnik, Nachrichtentechnik
:	English

:	318
:	Wasserzeichen
:	PC/MAC/eReader/Tablet
:	PDF

This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions

Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP. This is the first book published on this subject.

	TABLE OF CONTENTS	7
	FOREWORD	12
	PREFACE	14
	Open Verification Methodology	16
	Acknowledgements	16
	INTRODUCTION	18
	1.1 Assertion- Based IP	18
	1.2 Properties and assertions	26
	1.3 Who should read this book?	31
	1.4 Book organization	32
	1.5 Summary	34
	DEFINITIONS AND TERMINOLOGY	35
	2.1 Notation	36
	2.2 Verification component description	41
	2.3 Verification component organization	42
	2.4 Definitions	47
	2.5 Acronyms	51
	2.6 Summary	52
	THE PROCESS	53
	3.1 Guiding principles	54
	3.2 Process steps	55
	3.3 Assertion- based IP architecture	57
	3.4 Guidelines and conventions	73
	3.5 Summary	73
	BUS-BASED DESIGN EXAMPLE	74
	4.1 Bus- based design overview	75
	4.2 Summary	76
	INTERFACES	77
	5.1 Simple generic serial bus interface	78
	5.2 Simple generic nonpipelined bus interface	89
	5.3 Simple generic pipelined bus interface	103
	5.4 Interface monitor coverage example	122
	5.5 Summary	126
	ARBITERS	127
	6.1 Arbitrations schemes	128
	6.2 Creating an arbiter assertion- based IP	148
	6.3 Summary	156
	CONTROLLERS	158
	7.1 Simple generic memory controller	159
	7.2 Summary	187
	DATAPATH	189
	8.1 Multiport register file	191
	8.2 Data queue	210
	8.3 Data error correction	226
	8.4 Data compression	237
	8.5 Data decompression	251
	8.6 Summary	263
	QUICK TUTORIAL FOR SVA	265
	A. 1 SVA fundamentals	265
	A. 2 SystemVerilog sequences	270
	A. 3 Property declarations	275
	A. 4 Sequence and property operators	276
	A. 5 SVA system functions and task	280
	A. 6 Dynamic data within sequences	284
	A. 7 SVA directives	285
	A. 8 Useful named property examples	286
	COMPLETE OVM/AVM TESTBENCH EXAMPLE	287
	B. 1 OVM/ AVM Example Source Code	288
	B. 2 OVM/ AVM high- level reference guide	313
	BIBLIOGRAPHY	316
	Index	319